The present invention relates, in general, to semiconductor devices, and more particularly, to a method for forming a base link in a bipolar transistor.
Conventional lateral bipolar transistors commonly have a narrow base region in the center of the lateral active area of the device. The base region within the active area is considered the intrinsic base. Additionally, conventional lateral bipolar transistors include an extrinsic base portion which is typically a portion of a doped polysilicon layer above and offset from the intrinsic base region in the underlying active region of the device. The extrinsic base portion is typically coupled to the intrinsic base region with a vertical base link. The base link commonly comprises a vertical polysilicon spacer having composition similar to the extrinsic base portion.
Typically, the shape and orientation of the base link greatly influences the definition of the intrinsic base region. This is because the intrinsic base region within the lateral active area is formed integrally with the forming of the polysilicon spacer base link. Consequently, it is important that the formation of the base link be controllable and accurate so that a consistent base link and intrinsic base can be defined.
The base link is typically formed along a vertical wall defined by well known photolithographic processes. More specifically, the vertical wall is typically etched using a photoresist mask. A problem arises, however, when the bipolar transistors are only a small portion or component of a larger device. This is the case for BiCMOS devices, where the majority of transistors are MOS devices and relatively few are bipolar devices. Under such circumstances, the vast majority of the devices must be covered with photoresist during definition of the vertical wall for the base link.
Due to the chemistry of the photoresist, the high amounts of photoresist inhibit the etching of the vertical wall for the base link. The resulting wall tends to be substantially angled rather than vertical. It is difficult to form an effective base link along this angled wall.
An additional problem which arises in conventional lateral bipolar transistor fabrication relates to the oxide layer which typically separates the polysilicon extrinsic base layer from the lateral active region in the surface of the substrate. This oxide layer must be etched along with the overlying polysilicon layer when defining the wall for the base link. Conventionally, the wall is defined using a timed etch. Unfortunately, timed etches do not take into account potential slight composition differences from wafer to wafer, for example. Consequently, in some cases overetching occurs and a significant amount of the active layer below the oxide layer is removed.
What is needed is an improved process for defining a base link which does not result in a substantially angled wall upon which the base link must be formed. Furthermore, it would be desirable to avoid unwanted removal of the active layer due to overetching of the oxide layer which separates the polysilicon extrinsic base layer from the active layer.